A charge sharing–based switching scheme for SAR ADCs

This paper presents an energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed scheme employs charge recycling method to keep the capacitor arrays free of transitional energy between bit generations except reset phase. In comparison with the conventional switching scheme, the proposed one achieves 100% transitional energy saving without considering reset phase. In addition, configuration of a 10-bit SAR ADC shows that the proposed switching scheme reduces the capacitor area by 25% compared with the conventional switching scheme.     

Gastric Adenocarcinomas and Signet-Ring Cell Carcinoma: Unraveling Gastric Cancer Complexity through Microbiome Analysis—Deepening Heterogeneity for a Personalized Therapy

Gastric cancer (GC) is the fifth most prevalent cancer worldwide and the third leading cause of global cancer mortality. With the advances of the omic studies, a heterogeneous GC landscape has been revealed, with significant molecular diversity. Given the multifaceted nature of GC, identification of different patient subsets with prognostic and/or predictive outcomes is a key aspect to allow tailoring of specific treatments. Recently, the involvement of the microbiota in gastric carcinogenesis has been described. To deepen this aspect, we compared microbiota composition in signet-ring cell carcinoma (SRCC) and adenocarcinoma (ADC), two distinct GC subtypes. To this purpose, 10 ADC and 10 SRCC and their paired non-tumor (PNT) counterparts were evaluated for microbiota composition through 16S rRNA analysis. Weighted and unweighted UniFrac and Bray–Curtis dissimilarity showed significant community-level separation between ADC and SRCC. Through the LEfSe (linear discriminant analysis coupled with effect size) tool, we identified potential microbial biomarkers associated with GC subtypes. In particular, SRCCs were significantly enriched in the phyla Fusobacteria, Bacteroidetes, Patescibacteria, whereas in the ADC type, Proteobacteria and Acidobacteria phyla were found. Overall, our data add new insights into GC heterogeneity and may contribute to deepening the GC classification.     

ADC发泡剂尾渣回收碳酸钠的工艺研究

以ADC发泡剂的尾渣十水碳酸钠为原料,探究用重结晶法实现制备一水碳酸钠的绿色工艺。实验结果表明,蒸发温度85℃,结晶时间60min,母液套用2次,可提高碳酸钠的收率。     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

第三代红外焦平面探测器读出电路

对红外探测器不断增长和提高的需求催生了第三代红外焦平面探测器技术。根据第三代红外探测器的概念,像素达到百万级,热灵敏度NETD达到1 m K量级是第三代制冷型高性能红外焦平面探测器的基本特征。计算结果表明读出电路需要达到1000 Me-以上的电荷处理能力和100 d B左右的动态范围(Dynamic Range)才能满足上述第三代红外焦平面探测器需求。提出在像素内进行数字积分技术,以期突破传统模拟读出电路的电荷存储量和动态范围瓶颈限制,使高空间分辨率、高温度分辨率及高帧频的第三代高性能制冷型红外焦平面探测器得到实现。     

A high dynamic range analog-front-end IC for electrochemical amperometric and voltammetric sensors

A wide input range, compliant with electrochemical amperometric and voltammetric sensors analog-front-end (AFE) integrated circuit (IC) is proposed. The AFE employs current integrator (CI) and trans-impedance amplifier (TIA) to deal with the input current in the order of nA and μA separately, achieving the advantage of high dynamic range and high resolution. Input voltage is converted to current through a series of precise resistances, and detected by CI or TIA, which making the input voltage range is not limited by the power supply. An incremental sigma-delta ADC is employed to digitize the transferring signal, reducing the complexity and power dissipation. Compared to other alternatives, the AFE could handle current and voltage signals simultaneously, and input voltage range is not limited by power supply, showing high dynamic range and resolution. The AFE IC is fabricated in 0.18 μm 1P5M mixed-signal CMOS process, occupies an area of 3.2 mm×2 mm, the readout circuit has a dynamic range of 120 dB, consumes 4.2 mA.     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

8位高速低功耗流水线型ADC的设计技术研究

采用7级子ADC流水线结构设计了一个8位80MS/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第一级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第一级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比（SNR）为53dB,有效位数（ENOB）为7.98位,该ADC的芯片面积只有0.56mm2,典型的功耗电流仅为22mA。整个ADC性能达到设计要求。     

12位逐次逼近模数转换器关键设计技术研究

采用逐次逼近方式设计了一个12位的超低功耗模数转换电路。为减小整个ADC的芯片面积、功耗和误差,提高有效位数,对整个ADC的采样保持电路结构进行了精确的设计,重点考虑了其中的高精度比较器电路结构;对以上两个模块的版图设计进行了精细的布局。采用0.18μmCMOS工艺,该ADC的信噪比（SNR）为72dB,有效位数（ENOB）为11.7位,该ADC的芯片面积只有0.36mm2,典型的功耗仅为40μW,微分非线性误差DNL小到0.6LSB、积分非线性误差INL只有0.63LSB。整个ADC性能达到设计要求。